Physical Design Engineer, Senior to Staff Level
Core
Complete physical implementation of complex digital integrated circuits (ASICs/SoCs) from netlist to GDSII, ensuring timing, power, area, and reliability constraints.
Role type
Senior to Staff Physical Design Engineer
Builds
ASICs and SoCs for mobile and wireless applications
Domain
Semiconductor / VLSI Physical Design
Required skills
Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), DRC/LVS/ERC verification, Power optimization (IR drop/EM), Signal integrity analysis, Scripting (Tcl, Shell, Perl, Makefile)
Preferred skills
Knowledge of lower geometry technology nodes (12nm, 7nm, 5nm), Standard cell libraries, Memory macros
Technologies
Synopsys ICC2, Fusion Compiler, PrimeTime, StarRC, Redhawk, Siemens Calibre
Responsibilities
Execute full physical design flow including floorplanning, placement, CTS, and routing; Perform STA to identify and fix setup/hold violations; Run and resolve DRC, LVS, and ERC; Implement low-power design techniques and analyze IR drop/EM; Analyze and mitigate signal integrity issues; Develop and maintain scripts to automate design flows
Seniority
Senior to Staff, hands-on IC
