Principal SoC I/O Performance Architect
Core
Define and optimize I/O performance (bandwidth, latency, QoS) for next-generation SoCs using modeling, simulation, emulation, and post-silicon analysis to steer architecture decisions.
Role type
Principal I/O Performance Architect
Builds
Next-generation SoCs and platform technologies
Domain
Semiconductor / SoC Architecture / High-Performance Computing
Deliverable
production ML models
Required skills
SoC or I/O architecture, performance modeling (analytical, event-driven, transaction-level), simulation/emulation analysis, firmware/software performance, post-silicon validation, systems thinking, data-driven decision making
Preferred skills
High-performance I/O technologies (PCIe, CXL, NVLink, UCIe, AXI), C++/Python/SystemC modeling, automation/AI-assisted workflows, cross-team technical leadership
Technologies
PCIe, CXL, IOMMU/SMMU, UALink, Ethernet, InfiniBand, NVLink, UCIe, AXI, CHI, DMA engines, SystemC, TLM, C++, Python
Responsibilities
Define performance objectives and signoff criteria for SoC I/O subsystems; Build and apply performance models to evaluate architectural options; Analyze performance data from simulation, emulation, and post-silicon results; Create reusable workloads and benchmark flows; Partner with architecture, design, and validation teams; Develop automation and AI-assisted workflows
Seniority
Principal, strategy & mentorship
