RTL Design - Staff engineer
Core
Designing complex SoCs with a focus on RTL coding, logic design, micro-architecture, and low-power design.
Role type
Staff RTL Design Engineer
Builds
Complex System-on-Chip (SoC) designs
Domain
Semiconductor / Hardware Engineering
Required skills
Verilog/System-Verilog, Logic design, Micro-architecture, SoC design and integration, AMBA protocols (AXI, AHB, APB), USB/PCIE/SDCC peripherals, Memory controller design, Multi-clock designs, Asynchronous interfaces, Timing closure, Synthesis, ASIC tools (Lint, CDC, Design Compiler, Primetime)
Preferred skills
Microprocessor design, Pad ring creation, Chip-level floorplan collaboration
Technologies
Verilog, System-Verilog, Design Compiler, Primetime, Lint, CDC
Responsibilities
Develop constraints and achieve timing closure, Collaborate with verification and validation teams for pre/post Silicon debug, Design low-power SoCs, Work on multi-clock and asynchronous interface designs
Seniority
Staff, hands-on IC
