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ASIC Physical Design Engineer, Netlisting - New College Grad 2026

US, CA, Santa Clara💼 Full-time💰 $116,000–$116,000🗓 2026-05-07 → 2026-09-27

Core

Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block, cluster, and full chip levels, focusing on netlist-related aspects like equivalence checking, asynchronous checking, and logic synthesis.

Role type

ASIC Physical Design Engineer (Netlisting)

Builds

High-performance CPUs, GPUs, and SoCs for AI computing, gaming, and accelerated computing

Domain

Semiconductor / ASIC Design / AI Hardware

Deliverable

production ML models | product features

Required skills

Logic equivalence checking, Formal Verification, RTL/logic design, Clock-domain-crossing checking, MTBF analysis, Logic synthesis, EDA tools (Synopsys/Cadence), Scripting (Perl/TCL/Python)

Preferred skills

AI utilization for workflow improvement, Strong debugging capability

Technologies

Synopsys, Cadence, Perl, TCL, Make, Python

Responsibilities

Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs; Perform equivalence checking, asynchronous checking, and MTBF analysis; Assist in ECO generation and implementation

Seniority

Junior, New College Grad

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