Lead Physical Design Engineer
Core
Lead physical design and implementation of complex, high-performance semiconductor integrated circuits (AI NPUs) from RTL synthesis through timing convergence.
Role type
Lead IC physical design engineer (AI NPU)
Builds
High-performance semiconductor integrated circuits (AI NPUs)
Domain
Semiconductor / VLSI / AI Hardware
Deliverable
production ML models
Required skills
RTL synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis (STA), physical verification (DRC/LVS), power integrity analysis (IR drop/EM), scripting (Tcl/Perl/Python), deep sub-micron process technologies, VLSI design principles
Preferred skills
None stated
Technologies
Cadence Innovus/Genus/Tempus, Synopsys Fusion Compiler/PrimeTime, Mentor Calibre
Responsibilities
Execute physical design activities including floorplanning, power planning, place and route, CTS, and STA; Collaborate with physical verification and power integrity teams to resolve issues; Analyze and resolve design issues related to timing, area, and power; Develop and maintain scripts for automation and efficiency improvements; Contribute to the continuous improvement of physical design methodologies and flows; Generate comprehensive reports and documentation of design implementation
Seniority
Senior, hands-on IC
