HBM SoC Physical Design Engineer
Core
Drive implementation of advanced HBM SoC logic/base die designs from netlist to GDSII, ensuring best-in-class PPA and robust signoff for tape-out.
Role type
Senior IC physical design engineer (HBM SoC)
Builds
Heterogeneous Integration Group (HIG) HBM SoC products
Domain
Semiconductor / Memory / SoC Physical Design
Deliverable
production ML models | product features
Required skills
SoC physical design implementation, EDA tools (Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre), STA fundamentals, clocking, constraints, power intent (UPF/CPF), physical verification (DRC/LVS/ERC)
Preferred skills
HBM/DRAM adjacent SoC design, mentoring early-career engineers
Technologies
Cadence Innovus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, UPF, CPF
Responsibilities
Own physical implementation for SoC blocks and/or top-level (floor-planning, placement, CTS, routing, optimization); Drive timing closure across multi-mode/multi-corner scenarios; Integrate complex IP (controllers, NOC, interfaces, PHY-adjacent logic); Perform physical signoff (DRC/LVS, IR drop/EM, timing); Partner with DFT teams for scan/MBIST; Collaborate with packaging/assembly/test/manufacturing teams; Support tape-out execution and post-silicon debug; Identify flow gaps and improve productivity via scripting/automation
Seniority
Senior, hands-on IC
