Staff Engineer, GPU RTL Power Management
Core
Design and develop power management/SoC interface RTL blocks and subsystems for next-generation mobile GPU IPs to enable high-performance computing devices.
Role type
Staff GPU RTL Design Engineer (Power Management)
Builds
Microarchitecture definition and RTL implementation of power management GPU blocks and subsystems for mobile GPUs.
Domain
Semiconductor / Hardware Design / GPU Power Management
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), microarchitecture development, power management design, low power intent design, clock/reset control, clock domain crossing, dynamic voltage and frequency scaling, Python/Perl scripting
Preferred skills
GPU boot sequence firmware knowledge
Technologies
Verilog, SystemVerilog, Python, Perl
Responsibilities
Contribute to microarchitecture definition and RTL implementation of power management GPU blocks; drive design from microarchitecture through RTL development, integration, and debug; collaborate with verification teams to resolve functional issues and ensure coverage; address interface definition, timing, power, performance, and area tradeoffs; advance best practices by exploring emerging GPU technologies.
Seniority
Staff, hands-on IC
