Sr. ASIC Design Engineer
Core
Design high-speed ASICs from functional specifications to final netlist for cutting-edge networking chips used in routers and switches.
Role type
Senior IC ASIC Design Engineer
Builds
High-density networking silicon chips for HPE Networking routers and switches
Domain
Networking hardware / Semiconductor design
Deliverable
production ML models | product features
Required skills
Verilog/System Verilog, RTL design, micro-architecture specification, timing closure, functional coverage/SVA, Perl/Python
Preferred skills
Computer architecture knowledge, networking protocols, synthesis/lint tools, EDA tools, AI agentic tools
Technologies
Verilog, System Verilog, Perl, Python, EDA tools
Responsibilities
Produce detailed micro-architecture specifications meeting power/area requirements; implement designs in RTL; write functional coverage and SVA; collaborate with Physical Design for floorplan and timing closure; mentor new college-grad engineers and interns
Seniority
Senior, hands-on IC
