Principal ASIC Design Engineer
Core
Architect complex modules and subsystems for high-performance networking chips, defining micro-architecture specifications and implementing designs to meet power, area, and performance targets.
Role type
Principal ASIC Design Engineer (Networking)
Builds
High-performance networking chips and complex integrated circuit subsystems
Domain
Semiconductor / Networking / Hardware
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog/System Verilog, RTL design, micro-architecture specification, timing closure, power reduction techniques, cross-functional collaboration, technical leadership
Preferred skills
Computer architecture knowledge, networking protocols, synthesis/lint tools, Perl/Python
Technologies
Verilog, System Verilog, SVA, Perl, Python
Responsibilities
Architect complex modules and subsystems for high-performance networking chips; Write detailed functional and micro-architecture specifications; Implement designs using Verilog or System Verilog; Write functional coverage/SVA for verification; Optimize designs for power targets; Collaborate with physical design and verification teams; Mentor junior engineers and interns
Seniority
Principal, hands-on IC with technical leadership
