ASIC Implementation Engineer
Core
Physical Design Engineer responsible for taking Netlist to silicon tape-out for next-generation AI designs.
Role type
Senior IC physical design engineer
Builds
ASIC chips for AI applications
Domain
Semiconductor / VLSI
Deliverable
production ML models
Required skills
Physical Design, Physical Verification, Timing Closure, EM/IR Analysis, Place and Route, Clock Tree Synthesis, Floor-planning and Layout, Flow and Methodology Development, TCL/PERL Scripting, EDA Tools
Preferred skills
top-level STA, custom clock trees, insertion reduction, skew balancing, top-level floorplanning
Technologies
EDA Tools
Responsibilities
Execution of Physical Design, Physical Verification, and Timing Closure; EM/IR Analysis; Place and Route; Clock Tree Synthesis; Floor-planning and Layout; Flow and Methodology Development; Collaborating with IC Design RTL Engineers
Seniority
Senior, hands-on IC
