RTL Engineer
Core
Designing high-performance RTL for complex SoCs in AI-driven data centers and humanoid systems.
Role type
Senior RTL Engineer (SoC/MCU)
Builds
High-performance System-on-Chips (SoCs) for AI data centers and humanoid robotics
Domain
Semiconductor / Digital Design / Embedded Systems
Deliverable
production ML models | product features
Required skills
SystemVerilog, VHDL, digital design fundamentals (pipelining, state machines, bus protocols), synthesis tools (DC, Design Compiler, Innovus), static timing analysis, low-power techniques (clock gating, power-domain isolation), scripting (Tcl, Perl, Python, Bash), UVM verification flow
Preferred skills
RTL architecture definition, testbench creation and regression, timing constraint development (SDC), power-aware design, design review leadership, coding guideline establishment, post-silicon bring-up support
Technologies
SystemVerilog, VHDL, Tcl, Perl, Python, Bash, UVM, Design Compiler, Innovus, DC, SDC
Responsibilities
Define and implement RTL architecture for complex SoCs; Develop and maintain synthesizable SystemVerilog/VHDL code; Create and own RTL simulation and synthesis testbenches; Perform timing analysis, constraint development, and STA; Lead power-aware design techniques; Mentor junior RTL designers
Seniority
Senior, hands-on IC
