ASIC Physical Design Engineer
Core
Lead macro-level RTL-to-GDSII physical implementation and signoff for complex SoC and block-level projects, translating architecture into optimal physical design.
Role type
Senior IC ASIC Physical Design Engineer
Builds
Complex SoC and block-level ASIC chips
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII physical implementation, synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), routing, static timing analysis (STA), physical verification, formal verification, Electromigration (EM) analysis, IR-drop analysis, PPA optimization
Preferred skills
Physical design methodologies, LVS/DRC, EDA toolchains, Tcl/Python/Perl scripting
Technologies
Synopsys, Cadence
Responsibilities
Perform synthesis, floorplanning, placement, CTS, and routing; Optimize power, performance, and area (PPA); Execute static timing analysis (STA) and signoff closure; Analyze and resolve Electromigration (EM) and IR-drop issues
Seniority
Senior, hands-on IC
