SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)
Core
Architect, design, and implement RTL for SoC-level blocks and subsystems in next-generation HBM logic die, integrating memory IP and optimizing for power, performance, and area.
Role type
Senior IC SoC Architecture and Design Engineer
Builds
High-performance HBM SoC logic dies for memory and storage solutions
Domain
Semiconductor / Memory / SoC Design
Required skills
SystemVerilog, Verilog, SoC integration methodologies, RTL-to-GDS flow, EDA tools (Cadence, Synopsys, Siemens), Python/TCL/Perl scripting
Preferred skills
HBM/DRAM SoC design, high-speed interfaces, clocking strategies, DFT concepts, hardware emulation platforms
Technologies
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, Palladium, Veloce, Zebu
Responsibilities
Architect and design memory sub-systems including IP selection and bus/protocol selection; Integrate internal and third-party IP (controllers, NOC, RAS, MBIST); Translate architectural specs into high-quality RTL implementations; Participate in SoC-level integration (clocking, reset, power intent); Assist with pre-silicon validation and post-silicon bring-up; Collaborate with Product Engineering, Test, and Manufacturing teams
Seniority
Senior, hands-on IC
