SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)
Core
Architecting, designing, and implementing RTL for SoC-level blocks and subsystems in next-generation HBM logic die.
Role type
Senior IC SoC Architecture and Design Engineer
Builds
High-performance HBM SoC logic die for memory and storage solutions
Domain
Semiconductor / Memory and Storage
Deliverable
production ML models | product features
Required skills
SystemVerilog/Verilog, SoC integration methodologies, RTL-to-GDS flow, EDA tools (Cadence, Synopsys, Siemens), Python/TCL/Perl/shell scripting
Preferred skills
HBM/DRAM/memory-centric SoC designs, high-speed interfaces, clocking strategies, reset architectures, power management, DFT concepts, hardware emulation platforms
Technologies
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, shell scripting
Responsibilities
Architect and design memory sub-systems including IP selection and integration; Integrate internal and third-party IP; Translate architectural specifications into high-quality RTL implementations; Participate in SoC-level integration activities including clocking and power intent; Assist with pre-silicon validation and post-silicon bring-up; Contribute to design documentation and reviews; Collaborate with Product Engineering, Test, and Manufacturing teams
Seniority
Senior, hands-on IC
