Power and Performance Engineer, PAI Platforms and Performance Analysis
Core
Hands-on power and performance profiling of SoC platforms (pre/post-silicon) for robotics and automotive markets, defining TDP and automation harnesses.
Role type
Senior IC power and performance engineer (SoC)
Builds
Automation harnesses for workload execution, profiling, and telemetry; power/performance requirements for PAI products
Domain
Semiconductor hardware (SoC), embedded systems, robotics, automotive
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Pre-silicon or post-silicon power/performance analysis, heterogeneous compute systems (CPU/GPU/NPU/memory/interconnect), Linux-based device workload execution, automation harness development, power/thermal/performance trade-off analysis, profiling tools and performance counters, scripting and data analysis, translating workload behavior to engineering requirements
Preferred skills
Embedded robotics development platforms, platform performance analysis and silicon validation, automotive/robotics/edge AI workloads, TDP definition and thermal constraints, Arm architecture and Linux performance tools, benchmark automation and lab infrastructure, pre-silicon simulation/emulation/FPGA/virtual platforms, vendor telemetry tools and power analysers
Technologies
perf, ftrace, trace-cmd, sysfs, procfs, Python, shell scripting
Responsibilities
Perform hands-on power and performance profiling of SoC platforms across CPU, GPU, NPU/AI accelerator, memory, interconnect, and full-system workloads; Run benchmarks and real-world workloads on Linux-based devices, development boards, reference platforms, and pre/post-silicon environments; Develop and maintain automation harnesses for workload execution, profiling, telemetry, power measurement, and result analysis; Drive methodology for pre-silicon PnP analysis, including workload selection, benchmark definition, estimation, and correlation planning; Support post-silicon PnP analysis, including platform characterisation, bottleneck analysis, and power/performance trade-off analysis; Define TDP methodology for SoC products, linking workloads, sustained performance, peak power, thermal constraints, and product segments; Define power and performance requirements for PAI products in robotics and automotive markets; Produce clear technical reports and recommendations for architecture, product, software, systems, and platform teams
Seniority
Senior, hands-on IC