Emulation Engineer - Hardware Prototyping (HAPS)
Core
Own HAPS bring-up by taking RTL from design teams and getting it running on prototypes through partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly.
Role type
Senior IC emulation engineer (hardware prototyping)
Builds
Hardware prototypes for frontier intelligence inference workloads
Domain
AI infrastructure / Hardware prototyping
Deliverable
production ML models
Required skills
FPGA prototyping, SystemVerilog, Verilog, C/C++, Linux system development, Python, TCL, shell scripting
Preferred skills
ProtoCompiler, Vivado, Synopsys prototyping flows, emulation platforms (ZeBu, Palladium, Veloce), UVM verification, waveform debug tooling, cluster scheduling
Technologies
HAPS, Protium, proFPGA, S2C, PCIe, Ethernet, HBM, JTAG, I2C, UART, QSPI, Verdi, SimVision, SLURM
Responsibilities
Partition RTL and achieve multi-FPGA timing closure, enable new subsystem configurations for earlier software access, debug cross-FPGA issues using waveform capture and protocol analyzers, bring up interfaces (PCIe, Ethernet, HBM, JTAG, etc.), automate builds and image delivery flows, collaborate across design, DV, silicon validation, and firmware teams
Seniority
Senior, hands-on IC
