Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Core
Develop complex, highly integrated, low-power System on a Chip (SoC) architectures and digital subsystems for wireless IoT applications.
Role type
Staff Digital Design Engineer (SoC Low Power, Clocking & Integration)
Builds
Wireless MCU SoCs with embedded CPUs, analog/digital peripherals, security, and power management for smart home, industrial IoT, and smart cities.
Domain
Semiconductor / IoT / Low-power SoC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design (Verilog/System Verilog), SoC clocking architectures, low-power design methodologies (UPF, power gating), on-chip bus protocols (AXI, AHB, APB), SoC integration, digital CMOS IC design, Python/Perl/Tcl scripting, CDC/RDC techniques
Preferred skills
AI-powered tools for productivity, backend optimization for power/performance/area, analog/mixed-signal design support, revision control systems
Technologies
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, Perforce, Git, Methodics, Python, Perl, Tcl
Responsibilities
Develop complex SOC/chip architectures with multiple processors and power domains; Define and implement SoC-level low-power architecture; Drive RTL design and integration of power/clock/reset controllers; Lead small teams of design engineers; Analyze and debug low-power, clocking, and integration issues; Validate designs on silicon.
Seniority
Staff, hands-on IC with team leadership
