Principal RTL Design
Core
Lead the full RTL design lifecycle for high-quality DRAM digital and mixed-signal IP, delivering designs that meet aggressive power, performance, and area (PPA) targets.
Role type
Principal RTL Design Engineer (ASIC/SoC)
Builds
DRAM digital and mixed-signal IP cores
Domain
Semiconductor / Memory / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog/SystemVerilog, logic synthesis, static timing analysis (STA), UPF-based power intent, CDC/RDC, RTL design, mixed-signal interfacing
Preferred skills
DRAM architecture, advanced ASIC technology nodes, CMOS digital/analog concepts, system-level impact analysis
Technologies
Verilog, SystemVerilog, UPF, CDC, RDC, STA
Responsibilities
Own and drive RTL design from specification through silicon-ready signoff; Architect high-performance, power- and area-efficient RTL designs; Perform and sign off front-end quality checks (lint, synthesis, timing QoR); Collaborate with physical design, verification, and architecture teams; Refine methodologies and automation to improve design quality and efficiency
Seniority
Principal, hands-on IC with technical leadership
