Principal Physical Design Engineer
Core
Developing scalable RTL-to-GDS physical design flows and methodologies for advanced ASIC designs to ensure high-performance silicon delivery.
Role type
Principal Physical Design Flow and Place-and-Route (P&R) Development Engineer
Builds
Scalable P&R methodologies, automation infrastructures, and high-quality silicon implementations
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (RTL-to-GDS flows, P&R methodologies)
Required skills
Cadence Innovus, Synopsys Fusion Compiler, Tcl scripting, Python scripting, Linux shell, floor planning, placement, CTS, routing, timing closure, power grid planning, DRC/LVS signoff, IR/EM mitigation
Preferred skills
Advanced process nodes (7nm/5nm), UPF/low-power flows, hierarchical P&R, Git/Perforce, CI automation, STA signoff, parasitic modeling
Technologies
Innovus, Fusion Compiler, PrimeTime, StarRC, Voltus, RedHawk, Calibre, Tcl, Python, Make
Responsibilities
Develop and automate RTL-to-GDS flows; Partner with design teams for full-chip P&R execution; Debug tool issues and convergence challenges; Define physical signoff criteria and quality metrics; Evaluate new EDA tools and design methodologies
Seniority
Principal, hands-on IC with strategy & mentorship