SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)
Core
Architect, design, and implement RTL for SoC-level blocks and subsystems in next-generation HBM logic dies, focusing on memory sub-systems, IP integration, and power/performance/area optimization.
Role type
Senior IC SoC Architecture and Design Engineer
Builds
High-performance HBM SoC logic dies for memory and storage solutions
Domain
Semiconductor / Memory and Storage / SoC Design
Deliverable
production ML models | product features
Required skills
SystemVerilog/Verilog, SoC integration methodologies, RTL-to-GDS flow, EDA tools (Cadence/Synopsys/Siemens), Python/TCL/Perl/shell scripting
Preferred skills
HBM/DRAM memory-centric SoC design, high-speed interfaces, clocking strategies, DFT concepts, hardware emulation platforms
Technologies
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Palladium, Veloce, Zebu
Responsibilities
Architect and design memory sub-systems including IP selection and bus/protocol integration; Integrate internal and third-party IP (controllers, NOC, RAS, MBIST, PHY-adjacent logic); Translate architectural specifications into high-quality RTL implementations; Participate in SoC-level integration activities (clocking, reset, power intent); Assist with pre-silicon validation and post-silicon bring-up; Collaborate with Product Engineering, Test, and Manufacturing teams
Seniority
Senior, hands-on IC
