HBM Sr RTL Engineer
Core
Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die, integrating IP and supporting pre/post-silicon validation.
Role type
Senior IC RTL engineer (SoC/HBM)
Builds
Next-generation HBM SoC logic die
Domain
Semiconductor / Memory / SoC Design
Deliverable
production ML models | product features | infrastructure
Required skills
SystemVerilog, Verilog, SoC integration, RTL-to-GDS flow, synthesis, static timing analysis, scripting (Python/TCL/Perl/shell), debug (simulation/emulation/formal), clocking, reset, power intent
Preferred skills
HBM/DRAM SoC design, high-speed interfaces, DFT concepts (scan/MBIST/BIRA/BISR)
Technologies
SystemVerilog, Verilog, Python, TCL, Perl, shell scripting
Responsibilities
Design RTL for SoC blocks; Integrate internal and third-party IP; Collaborate with architects on specifications; Participate in clocking, reset, and power intent integration; Debug simulation, emulation, and formal results; Work with physical design teams on timing and power; Assist with pre-silicon validation and post-silicon bring-up; Contribute to design documentation and reviews.
Seniority
Mid-level, hands-on IC
