Principal Engineer - CAD, SoC Floorplan and Advance Technode
Core
Developing scalable methodologies and automation for next-generation SoC floor-planning, power delivery network (PDN) design, and technology-node-aware implementation for high-performance, low-power multi-die systems.
Role type
Principal Engineer, SoC Floorplan and Advanced Technology Node
Builds
Tool-flow-methodology and automation for hierarchical and multi-die SoC implementations
Domain
Semiconductor / EDA / Physical Design
Deliverable
production ML models | product features | infrastructure
Required skills
SoC design flow automation, hierarchical floor-planning, PDN design, Python scripting, C programming, EDA tools, Git, low-power design methodologies, UPF-based design, physical verification flows
Preferred skills
Advanced clocking structures, power delivery optimization, physical verification convergence, AI-assisted design automation
Technologies
Python, C, Git, EDA tools
Responsibilities
Develop advanced SoC floor-planning methodologies for complex hierarchical and multi-die designs; Define and optimize PDN implementation including IR/EM-aware planning and power integrity; Build scalable automation for top-level floor-planning, power mesh, clocking, and IO/IP integration; Drive methodology innovations for advanced technology nodes and chiplet systems
Seniority
Principal, hands-on IC