SR RTL DESIGN
Core
Design and develop high-performance, power- and area-efficient RTL for digital and mixed-signal DRAM blocks from specification to signoff.
Role type
Senior RTL Engineer (ASIC/DRAM)
Builds
DRAM digital and mixed-signal blocks for advanced memory products
Domain
Semiconductor / Memory / ASIC Design
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog, ASIC low-power design methodologies, UPF-based power intent, CDC/RDC analysis, logic synthesis, static timing analysis, RTL-to-GDS flows
Preferred skills
Mixed-signal-interfacing RTL development, CMOS digital and analog-integrated circuit concepts, memory or high-performance digital design experience
Technologies
RTL simulation tools, UPF, CDC/RDC, STA
Responsibilities
Contribute to RTL build of digital and mixed-signal components using RTL-to-GDS flows; Implement and document high-performance, power- and area-efficient RTL designs; Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR; Collaborate with physical design teams to achieve timing closure and PPA goals; Apply power-, clock-, and implementation-aware RTL design practices to minimize silicon risk.
