Senior Principal Physical Design Engineer
Core
Lead and execute advanced physical design activities for complex SoC and IP blocks, achieving performance, power, and area targets for cutting-edge semiconductor products.
Role type
Senior Principal IC physical design engineer
Builds
Large-scale digital designs (RTL to GDSII) for semiconductor products
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (SoC/IP blocks)
Required skills
ASIC physical design, floor planning, power planning, place and route, clock tree synthesis, static timing analysis (STA), formal verification, DRC, LVS, low-power design techniques, EDA tool integration, scripting automation, semiconductor physics, DFM principles
Preferred skills
Mentorship of junior engineers, defining design specifications from physical implementation perspective
Technologies
Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, Ansys RedHawk/PathFinder, Tcl, Perl, Python
Responsibilities
Lead physical design execution from RTL to GDSII, optimize design flows and scripts, perform critical path analysis, collaborate with design/architecture/verification teams, mentor engineers, evaluate new EDA tools, develop low-power techniques, generate design documentation
Seniority
Senior, hands-on IC with mentorship responsibilities