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Hardware & Physical Engineering
› Analog IC Design
Analog IC Design
2,189 open positions
Lead Principal Engineer, Layout Design
Micron
Tlaquepaque, Jalisco, Mexico
6mo
Lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts.
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Senior Mixed Signal Design Engineer
NVIDIA
Taiwan, Taipei
6mo
Designing high-speed memory I/O interfaces and solving circuit design challenges in deep submicron CMOS FinFET processes for NVIDIA's GPU and AI products.
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Custom Silicon Management Analog Design Lead - Sensors
Apple
San Diego, United States of America
6mo
Lead the definition, development, and productization of next-generation sensor solutions (Touch, Optical, Motion, Health) for mobile products.
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Custom Silicon Management Analog Design Lead - Sensors
Apple
Cupertino, United States of America
6mo
Lead the definition, development, and productization of next-generation sensor solutions (Touch, Optical, Motion, Health) for mobile products.
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Lead Principal Engineer, Layout Design
Micron
Jalisco, Mexico
6mo
Lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts.
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Photonic Design Automation Engineer
PsiQuantum
Palo Alto, California, United States
$130k
6mo
Own and scale the layout-to-netlist and multi-physics integration flow for a silicon photonics platform to enable reliable photonic IC tape-outs.
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Senior EM/IR Engineer
Espace
Saratoga, CA
6mo
Design, simulate, and verify high-performance digital, analog, and RF integrated circuits for 5G, IoT, and satellite communications applications.
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Senior Engineer - Standard Cell Design
Micron
Hyderabad - Phoenix Aquila, India
6mo
Design and maintain standard cells for new DRAM products on new technology, collaborating with DTCO teams to develop architectures and characterization models.
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Your Next Career Opportunity at Infineon Padova – Categorie Protette (ex art.1 L.68 /99) (f/m/div)
Infineon
Padua (Padova) (Italy)
6mo
Join Infineon's R&D Center in Padova to contribute to the full product development cycle of cutting-edge automotive chips.
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Staff Engineer Design
Micron
Hyderabad - Phoenix Aquila, India
6mo
Block and sub-system level design and timing optimization for memory and storage solutions, supervising layout and collaborating on full-chip floorplanning.
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Mixed Signal Logic Design Engineer
Intel
Malaysia, Penang
6mo
Develops logic design, RTL coding, and simulation for mixed-signal and high-speed IPs to generate cell libraries, functional units, and subsystems for full chip integration.
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Staff Engineer Design
Micron
Hyderabad, Telangana, India
6mo
Lead block and sub-system level design, timing optimization, and full-chip floorplanning for memory and storage solutions.
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Field Application Engineer Intern (Hardware)
Marvell
Shanghai
6mo
Intern supporting customer engagements, debugging hardware/software systems, and optimizing optical interconnect product performance.
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Senior Engineer, Analog Layout
Renesas-Electronics
Remote
6mo
Senior Analog Layout Engineer developing floor plans, routing, and verification for PMICs, Linear, and Switching DC-DC converters powering next-gen phones and handheld devices.
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Senior Mask Design Engineer - Hardware
NVIDIA
US, CA, Santa Clara
$132k
6mo
Senior Mask Layout Design Engineer performing physical layout for high-speed mixed-signal circuits (PLLs, SerDes, ADCs, ESD) in sub-micron CMOS technologies.
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Layout Designer
Texas Instruments
Tucson, AZ, United States
6mo
Development and preparation of multi-dimensional layouts and detailed drawings of semiconductor devices from schematics and geometry.
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Senior Mixed Signal Design Engineer
NVIDIA
US, CA, Santa Clara
$168k
6mo
Senior engineer developing high-speed electrical/optical interfaces and analog circuits for next-generation NVLINK, supporting products from consumer graphics to self-driving cars and AI.
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Electrical/Optical SerDes Analog Mixed Signal Design Engineer
MediaTek
Irvine, CA
6mo
Design and verification of high-speed electrical and optical transceivers for data centers, cloud infrastructure, and AI/HPC systems.
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Senior Mixed Signal Design Engineer
NVIDIA
US, CA, Santa Clara
$168k–$265k
6mo
Design high-speed electrical/optical interfaces and analog circuits for next-generation NVLINK, taking designs from concept through silicon characterization.
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Principal Analog Layout Engineer
Ciena
Ottawa
CA$138k
6mo
Develop block and macro level layouts for high-speed analog circuits (DAC, ADC, SERDES) in deep-submicron CMOS/BiCMOS technologies for optical fiber transmission solutions.
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ENGR STAFF, ANALOG; DSGN
ON Semiconductor
Bangalore, Karnataka, India
6mo
Design and develop high-performance, reliable non-volatile memory (NVM) IPs for automotive and industrial systems.
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CMOS Device Integration Team - DMTS
Micron
Boise, ID - Main Site
6mo
Leading CMOS device and module development for next-generation DRAM, HBM, and Compute-in-Memory architectures to enable AI and high-performance computing.
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Foundry Virtuoso Engineer
Cadence
SHANGHAI 08
6mo
Provide technical support for Virtuoso-based analog backend flows, including schematic, layout, and design environment usage, while assisting foundry teams in developing and maintaining technology files and PCells.
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SI/PI Engineer
Etched
San Jose
6mo
Own SI/PI methodology for high-speed PCB and system designs ensuring electrical margins for multi-gigabit interfaces.
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Power Integrity Engineer
Apple
San Francisco Bay Area, United States of America
6mo
Develop, implement, and verify Power Integrity solutions for System-on-Chip (SoC) power delivery networks across die, interposer, package, and board levels for Apple devices.
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Lead Customer Engagement Engineer - Voltus
Cadence
SHANGHAI
6mo
Enables EM/IR and thermal signoff technologies for Foundry PDK and Design Service teams through techfile development and reference flow creation.
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Analog Engineer Intern - PhD
Marvell
Ottawa, Canada
CA$75k–CA$100k
6mo
Design and validation of FET and BiCMOS circuits for high-speed broadband ICs serving data center, metro, and long-haul fiber optic communication applications.
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Analog Engineer Intern - PhD
Marvell
Vancouver, Canada
CA$75k–CA$100k
6mo
Design and verify analog IP blocks for DSP transceivers within the Central Engineering business group.
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Sr Layout Engineer
Monolithicpower
Barcelona, Spain
6mo
Lead IC layout activities from floorplanning through tape-out for integrated power semiconductors.
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Analog Engineer Intern - PhD
Marvell
Toronto, Canada
CA$75k–CA$100k
6mo
Support the analog design team in architectural exploration and circuit implementation for high-speed optical transceivers (PLLs, DLLs, ADCs, regulators, amplifiers, TX/RX).
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Power & Performance Engineer - Platform Architecture
Apple
Santa Clara, United States of America
6mo
Analyze silicon to extract intelligence on process technology, circuit design, memory architectures, and logic efficiency to inform Apple's silicon roadmap.
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IO/ESD Layout Engineer (Senior/Staff)
MediaTek
Singapore
6mo
Physical implementation of custom integrated circuitries including IO/ESD, Standard Cells, Memory Compilers, Analog IP, and RF building blocks for advanced semiconductor technology.
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RF Technology Development Device Engineer - MTS
GlobalFoundries
Essex Junction
$98k
6mo
Develop and optimize SiGe HBTs and RF CMOS devices using TCAD simulation, electrical characterization, and process integration for RF technology.
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Analog IC Design Manager m/f/d
Texas Instruments
Freising, Bayern, Germany
6mo
Lead mixed-signal IC design and layout teams to bring precision ICs integrating high-resolution ADCs, DACs, amplifiers, references, data communication, and power management to market.
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(Senior) PIC Design Engineer - Architecture & Fiber Coupling (f/m/d)
Q Ant Gmbh
Stuttgart
6mo
Design, development, and optimization of advanced photonic integrated circuit (PIC) components, with a specific focus on fiber-to-chip coupling and photonic packaging for AI computing systems.
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SMTS Product Architect
Micron
Boise, Idaho, United States of America
$177k
6mo
Define electrical architecture for next-generation DRAM products, focusing on Signal Integrity (SI) and Power Integrity (PI) to enable high-performance computing and AI platforms.
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ENGR SR, PRODUCT; PROD & TEST
ON Semiconductor
Bangalore, Karnataka, India
6mo
Drive development, validation, and mass production of mixed-signal image sensors from definition to market release.
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LPDDR Layout Design Engineer
Micron
Hashimoto, Japan
6mo
Designing and analyzing digital and analog circuits for memory products, overseeing layout processes including floor-planning, placement, and routing.
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Sr Engineer, Memory CAD, Guadalajara
Micron
Tlaquepaque, Jalisco, Mexico
6mo
Support CAD tools, flows, and collateral for HBM design teams while collaborating on mixed-signal, transistor-level custom IC design capabilities.
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STAFF ENG-HIG-HBM-LAYOUT
Micron
Hyderabad, Telangana, India
6mo
Lead the layout design and development of complex analog, mixed-signal, and digital blocks and full chip level integration for memory and storage solutions.
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Board Design Engineer, LDE - New College Graduate
NVIDIA
Taiwan, Taipei
6mo
Design new products for NVIDIA GPUs, DPUs, and CPUs covering Graphics, Self-driving, Servers, and Data centers, managing design execution from initial testing to manufacturing release.
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CPU circuit robustness management engineer
MediaTek
HsinChu
6mo
Review CPU IP pre-silicon circuit design weaknesses and develop post-silicon test items to screen circuit weaknesses.
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Senior Circuit Design Engineer - Power
NVIDIA
US, CA, Santa Clara
$168k–$265k
6mo
Designing and optimizing power delivery solutions for System-on-Chip (SoC) architectures to improve energy efficiency and address thermal, noise, and packaging constraints.
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Design Engineer
Micron
Hyderabad, Telangana, India
6mo
Design and optimize Memory/Logic/Analog circuits for new product opportunities.
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Engineer, HIG-HBM Product & System Engineering (Media Health Manufacturing)
Micron
Fab 10A, Singapore
6mo
Drive manufacturing test flow development, validation, and yield improvement for next-generation High Bandwidth Memory (HBM) products including DRAM, interface, and stacked die.
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Principal Thermal Mechanical Photonic Designer
NVIDIA
US, CA, Santa Clara
$232k
6mo
Designing thermal and structural solutions for Silicon Photonic chips and electronic packages to ensure reliability under stress and thermal conditions.
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MTS Packaging Integration Engineer
GlobalFoundries
USA - Vermont - Essex Junction
$94k
6mo
Deliver industry-leading electro-optical transceivers using GF's Photonix platform and advanced 2.5D/3D co-packaged optics form factors, focusing on tool-process interactions for SiPh Flip Chip assembly and module reliability.
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Signal Integrity Engineer – Memory Interface
Apple
San Diego, United States of America
6mo
Develop signal and power integrity for memory interfaces in Apple SoCs from package to board level.
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Mixed-Signal IC Design Engineer
Apple
Cupertino, United States of America
6mo
Design, develop, and verify analog and mixed-signal circuits and sub-systems for Apple integrated circuit devices, including transistor-level analog circuits, mixed-signal interfaces, and digital control blocks.
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PLL Design Engineer
Apple
Austin, United States of America
6mo
Designing cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies.
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