Principal Analog Layout Engineer
Core
Develop block and macro level layouts for high-speed analog circuits (DAC, ADC, SERDES) in deep-submicron CMOS/BiCMOS technologies for optical fiber transmission solutions.
Role type
Principal Analog Layout Engineer
Builds
High-speed analog macros (DAC, ADC, transimpedance amplifiers, modulator drivers) for coherent fiber-optic product solutions
Domain
Telecommunications / High-speed Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Custom analog and mixed-signal layout design, deep sub-micron CMOS device knowledge (Finfet), floor planning, device matching, parasitic minimization, EM/IR drop analysis, DRC/ANT/LVS/PERC verification, scripting (PERL/SKILL), semiconductor manufacturing process familiarity
Preferred skills
Experience with 112G/224G SERDES, advanced process effects (LOD, OSE, WPE), guard ring design, high-frequency routing techniques
Technologies
Cadence Virtuoso, Siemens Calibre, Ansys Totem
Responsibilities
Develop block and macro level layouts including floor-planning, placement, routing and optimization; Carry out layout feasibility studies on various circuit designs; Write automation scripts for layout flow improvements including pcells; Conduct thorough verification checks such as DRC, ANT, LVS, PERC, EM, IR; Debug ESD violations reported by PERC; Investigate new features within the layout tools and processes; Mentor junior layout team members
Seniority
Senior, hands-on IC
