Senior Mask Design Engineer - Hardware
Core
Senior Mask Layout Design Engineer performing physical layout for high-speed mixed-signal circuits (PLLs, SerDes, ADCs, ESD) in sub-micron CMOS technologies.
Role type
Senior IC mask layout engineer (mixed-signal)
Builds
High-speed mixed-signal circuit layouts for VLSI products
Domain
Semiconductor hardware design / Analog circuit layout
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog circuit layout concepts, Cadence custom circuit design tools, DRC/LVS checking flows, scripting (Perl/Python), verification tools (Dracula/Hercules/Calibre/Primeyield)
Preferred skills
None stated
Technologies
Cadence, Dracula, Hercules, Calibre, Primeyield, Perl, Python
Responsibilities
Perform physical layout for mixed-signal functions, work with ASIC and mixed-signal engineers for design integration, take part in floor planning and custom layout, verify against design rules and schematics
Seniority
Senior, hands-on IC
