Lead Principal Engineer, Layout Design
Core
Lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts.
Role type
Lead Principal Engineer, Layout Design
Builds
Custom IC layouts for memory products (DRAM, mixed-signal)
Domain
Semiconductor / Memory / Analog & Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (IC Layout)
Required skills
Custom IC layout, Physical verification, EDA tools, Scripting/automation, CMOS device understanding, Reliability checks, Tapeout execution, Floorplanning, Signal integrity analysis
Preferred skills
Advanced-node layout knowledge, Memory/storage technology trends, Debug skills, Multi-task prioritization
Technologies
EDA tools, Custom IC layout tools, Physical verification tools
Responsibilities
Lead layout build and physical realization of new memory products; Interpret device and circuit specifications to implement custom layout solutions; Develop hierarchical layouts for analog, digital, and memory-array circuitry; Build block and top-level floorplans optimizing placement, routing, and signal integrity; Run and debug physical verification flows and ensure closure; Lead resource planning, priorities, and tapeout schedules across multiple blocks.
Seniority
Principal, hands-on IC design with technical leadership