SI/PI Engineer
Core
Own SI/PI methodology for high-speed PCB and system designs ensuring electrical margins for multi-gigabit interfaces.
Role type
Senior IC Signal Integrity and Power Integrity Engineer
Builds
High-speed PCBs and system designs for inference-focused AI hardware
Domain
Hardware infrastructure for frontier intelligence (AI/ML accelerators)
Deliverable
production ML models
Required skills
SI/PI simulation (pre/post-layout), channel analysis, link budget calculations, PDN design and analysis, DFI and design rule checks, transmission line theory, lab measurement techniques (VNA, TDR, BERT, oscilloscope), EDA tool proficiency (Cadence Sigrity, Ansys SIwave/HFSS, Keysight ADS), multi-layer PCB stack-up design, controlled-impedance trace routing
Preferred skills
Data center/AI/ML accelerator/HPC hardware experience, automated simulation scripting (Python/MATLAB)
Technologies
Cadence Allegro, Sigrity, Ansys SIwave, HFSS, Keysight ADS, PCIe Gen5/Gen6, 112G/224G Ethernet, DDR4/5, HBM3/4
Responsibilities
Perform pre- and post-layout SI simulations for high-speed serial interfaces; Conduct channel analysis and link budget calculations; Develop and maintain COM, IBIS, S-parameter, and SPICE models; Execute power delivery network (PDN) design and analysis; Drive DFI and design rule checks for SI/PI compliance; Collaborate with PCB design and layout engineers and ASIC teams; Support bring-up, debug signal quality issues, and document root-cause findings; Develop and maintain simulation-to-hardware correlation databases
Seniority
Senior, hands-on IC
