Senior Engineer - Standard Cell Design
Core
Design and maintain standard cells for new DRAM products on new technology, collaborating with DTCO teams to develop architectures and characterization models.
Role type
Senior IC standard cell design engineer (DRAM)
Builds
Standard cell libraries and timing/power models for DRAM products
Domain
Semiconductor manufacturing / DRAM memory / Analog & Digital IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CMOS circuit design, CMOS device physics, standard cell flow (DTCO to lib release), RTL/GDS flow setup, block level timing analysis, ICC2, Finefet, Tanner Planner, characterization tools (Siliconsmart/Liberate), Cadence Virtuoso, Primetime, Solido Analytics, HSPICE, HSIM, VerilogHDL, FINESIM, Simvision, Standard cell layout and verification, Skill, TCL, Perl, Python
Preferred skills
Synopsys EDA flow, analog/digital simulation tools, AI-assisted tools for design and characterization
Technologies
ICC2, Finefet, Tanner Planner, Siliconsmart, Liberate, Cadence Virtuoso, Primetime, Solido Analytics, HSPICE, HSIM, VerilogHDL, FINESIM, Simvision, Skill, TCL, Perl, Python
Responsibilities
Design and maintain standard cells for new DRAM products, characterize and model standard cells for timing/power, analyze liberty models for performance/power/functionality, develop automation test benches and flows, collaborate on new flows and tools, identify design pain points for AI-based automation
Seniority
Senior, hands-on IC