Senior Engineer, Analog Layout
Core
Senior Analog Layout Engineer developing floor plans, routing, and verification for PMICs, Linear, and Switching DC-DC converters powering next-gen phones and handheld devices.
Role type
Senior IC analog layout engineer
Builds
Power management ICs (PMICs), Linear regulators, Switching DC-DC converters
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, Floor plan development, DRC/ERC/LVS verification, Automation scripting (TCL, PERL), Deep submicron CMOS processes, CAD tools (Virtuoso XL, Calibre), Mentorship
Preferred skills
None stated
Technologies
Virtuoso XL, Calibre DRC, Calibre LVS, Calibre PEX, VCAR, VSR, PVS, R3D
Responsibilities
Drive best practices for floor plan development and review; Use state-of-the-art layout techniques for matching accuracy and yield optimization; Implement automation to improve turnaround times; Perform routing and verification (DRC, ERC, LVS); Organize layout reviews and track project progress; Mentor junior layout engineers; Resolve CAD/PDK/process issues; Suggest improvements to methodology and procedures.
Seniority
Senior, hands-on IC with mentorship responsibilities
