IO/ESD Layout Engineer (Senior/Staff)
Core
Physical implementation of custom integrated circuitries including IO/ESD, Standard Cells, Memory Compilers, Analog IP, and RF building blocks for advanced semiconductor technology.
Role type
Senior/Staff Custom Layout Engineer
Builds
Custom IC layouts and physical implementations for AI chips
Domain
Semiconductor / Integrated Circuit Design
Deliverable
production ML models | product features | infrastructure
Required skills
Custom layout design, floorplanning, physical verification, QA flow sign-off, project status reporting, execution risk management
Preferred skills
Foundation IP development, Analog IP, RF building blocks
Technologies
Custom Layout tools, Physical Verification tools
Responsibilities
Realize physical implementation of circuitries including IO/ESD, Standard Cells, Memory Compilers, Analog IP, and RF building blocks; assume full responsibility for the complete layout implementation process including floorplanning, layout construction, and physical verification; provide timely project status updates and anticipate execution pitfalls to ensure on-time delivery