Analog Engineer Intern - PhD
Core
Design and verify analog IP blocks for DSP transceivers within the Central Engineering business group.
Role type
Analog IC Design Intern (PhD/MS level)
Builds
Analog IP blocks for DSP transceivers
Domain
Semiconductor, Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Transistor-level circuit design, Device physics, Feedback and loop stability analysis, Schematic capture, Layout design, Circuit simulation
Preferred skills
None stated
Technologies
Cadence Virtuoso
Responsibilities
Understand product requirements and block integration, Take ownership of a block for delivery, Evaluate circuit topology tradeoffs, Perform schematic capture and layout, Run schematic and post-layout simulations, Document design and hold design reviews, Design, simulate, and support analog IP verification
Seniority
Intern, PhD or MS student