Lead Principal Engineer, Layout Design
Core
Lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts.
Role type
Lead Principal Engineer, Layout Design
Builds
Custom IC layouts for memory products (DRAM, mixed-signal) optimized for PPA and reliability
Domain
Semiconductor / Memory and Storage / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CMOS device understanding, layout-dependent effects knowledge, custom IC layout, physical verification tools, reliability checks, tapeout leadership, scripting/automation
Preferred skills
Advanced-node layout considerations, memory/storage technology trends, problem-solving, debug skills
Technologies
EDA tools, physical verification flows, parasitic extraction tools
Responsibilities
Lead layout build and physical realization, interpret device/circuit specs for custom solutions, develop hierarchical layouts, build block/top-level floorplans, optimize for die size/matching/timing, run/debug physical verification flows, lead resource planning and tapeout schedules
Seniority
Principal, hands-on IC with strategic oversight