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Software Engineering
› Hardware Verification
Hardware Verification
796 open positions
Frontend Central Process Integration Senior Engineer
Micron
Boise, ID - ID1
5mo
Drive best-in-class product maturity, yield, and quality for global DRAM and NAND manufacturing by identifying, aligning, and deploying optimized process integration solutions across the network.
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Front End Central Product Integration (FE cPIE) Senior Manager
Micron
Taichung - Fab 16, Taiwan
5mo
Lead PI loop structural uniformity integration and cross loop integration projects for critical loops such as Capacitance loop to address yield and quality challenges in semiconductor manufacturing.
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Engineer, DEG Mobile DRAM Verification
Micron
Hyderabad - Phoenix Aquila, India
5mo
Senior Verification Engineer responsible for end-to-end analysis and verification of sophisticated full-chip gate-level custom designs for DDR5, LPDDR5, DDR6, and LPDDR6 memory architectures operating at speeds up to 9600MT/s.
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Staff Engineer - Design Verification
Micron
Hyderabad - Phoenix Aquila, India
5mo
Lead design verification activities for DRAM products, leveraging AI-based tools and automation to accelerate verification cycles and improve debug efficiency.
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Senior Engineer - Design Verification
Micron
Hyderabad - Phoenix Aquila, India
5mo
Develop and maintain verification activities for DRAM design, focusing on accelerating verification cycles and improving debug efficiency using AI-based tools and automation frameworks.
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Physical Design Backend STA Engineer
NVIDIA
Israel, Yokneam
5mo
Perform advanced Static Timing Analysis (STA) at chiplet and FC level to ensure timing convergence and quality approval for high-speed communication devices.
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Senior DFT Consultant (Tessent)
Siemens-Eda
Remote
$147k–$293k
5mo
Design for Test Consultant supporting the use of Tessent DFT software in the design of complex ASIC designs, implementing and verifying DFT features for enterprise customers.
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Lead Software Engineer ( Verification )
Cadence
BANGALORE
5mo
Developing Cadence software-driven verification solutions for electronic design architectures and IPs.
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Staff GenAI Engineer - AMS Design and Optimization
Micron
San Jose, CA
$170k–$170k
5mo
Embed AI and automation into circuit design, layout, verification, and optimization workflows to reduce manual effort and accelerate time-to-tapeout for memory products.
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Software Intern
Cadence
SAN JOSE
$0k–$0k
5mo
Software intern role focused on research and development of on-chip in parasitic modeling using state-of-the-art machine learning technologies.
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Senior/Staff Engineer, Frontend Labor Productivity & Data Engineering
Micron
Hiroshima - Fab 15, Japan
5mo
Drive measurable outcomes in labor productivity and annualized hour savings by implementing strategies focused on standardization, simplification, automation, and leveraging generative AI methodologies.
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Principal/Senior Principal Engineer – Arm ARM
Arm
Cambridge, United Kingdom
5mo
Lead the delivery and evolution of the Arm Architecture Reference Manual (Arm ARM), ensuring architectural intent is accurately communicated and the product maintains high quality, correctness, and accessibility.
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Engineer, Process Development (Core Engineering Module)
Micron
MSB, Singapore
5mo
Engineer responsible for integrating AI tools into daily work, executing NPI product qualifications, and leading continuous improvement of assembly processes to ensure high yield and cost efficiency in semiconductor manufacturing.
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Package Development Engineering – Product Integration Engineer (PDE PIE)
Micron
MSB, Singapore
5mo
Integrate AI-assisted tools into daily work, drive New Product Introduction (NPI) processes, and act as a technical integrator across manufacturing sites to bring new semiconductor packages into volume production.
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Principal EDA Software Engineer (C++, Characterization)
Cadence
SAN JOSE
$137k–$137k
5mo
Develop and enhance transistor-level analysis tools for static and dynamic circuit characterization, enabling timing, power, noise, and reliability analysis for advanced custom digital and mixed-signal circuits.
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Senior Product Applications Engineer - Interconnects
Ciena
Ottawa
$112k–$112k
5mo
Senior Product Applications Engineer developing reference designs, API suites, and lab testing solutions for coherent optical modules and components to support customer integration and design wins.
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DFT Intern
Etched
San Jose
5mo
Review and refine DFT flow automation to support chip-level regression on Caelius, contributing to DFT verification and developing flows for ATPG fault models.
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Software Engineer - Platform Technologies
Sifive
Austin, Texas, United States
5mo
Develop and maintain core tools and flows for microprocessor design, including simulation and build tools to validate designs.
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Design Verification Infrastructure Engineer - Software
Sifive
Hsinchu, Taiwan
5mo
Develop and maintain the Verification Platform libraries and tools used across SiFive for Design Verification and validation activities.
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Senior RTL Design Engineer - CPU Frontend
Sifive
Santa Clara, California, United States
$159k–$159k
5mo
Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
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ENGINEER, UNIFORMITY PROCESS DEV
Micron
Fab 10N/X, Singapore
5mo
Develop and transfer regE processes for next-generation 3D NAND nodes, focusing on process margin improvement, wafer edge defect resolution, and manufacturability for high-volume manufacturing.
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Senior Member Technical Staff
Siemens-Eda
Bangalore, IND, India
5mo
Design and development of RTL synthesis technology, logic optimizations, and low power synthesis for complex digital IC designs.
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Analog EDA Backend Lead
Texas Instruments
Bengaluru, Karnataka, India
5mo
Lead EDA solutions development, vendor tool evaluation, and PDK usage support for TI's internal and external design teams.
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Senior Integration/API architect
PsiQuantum
Palo Alto, California, United States
5mo
Design and scale the integration architecture connecting photonic IC, passive, and active IC design toolchains for a silicon photonic quantum computer.
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Director, Software Manufacturing
Lumilens
San Jose
5mo
Lead strategy and execution of software systems enabling high-volume manufacturing of next-generation optical transceivers (800G, 1.6T+), driving yield, test, calibration, and production efficiency.
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CAE電腦輔助自動化軟體工程師 (林口園區)
AdvanTech
Linkou
5mo
Responsibilities: Develop PCB Layout automation processes using SKILL language in Cadence EDA Tool to replace manual tasks; Build automated program editing architecture using AI technology; Develop and maintain Layout management system using PHP.
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Engineer, Product & System Engineering (Media Health Reliability), Heteregenous Integration - High Bandwidth Memory
Micron
Fab 10A, Singapore
5mo
Drive intrinsic and extrinsic reliability test development and execution for High Bandwidth Memory (HBM) products, focusing on DPM reduction and root cause analysis for defectivity and reliability failures.
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Photonic IC Development Tech Lead
MediaTek
San Jose, CA
5mo
Leading the end-to-end development and design platform for high-volume silicon photonics integrated circuits (PICs), establishing methodology for device design, integration, and production ramp.
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Staff Digital Design Engineer
ON Semiconductor
Bangalore, Karnataka, India
5mo
Designing and verifying digital processing blocks for CMOS Image Sensors used in automotive and industrial applications.
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IC Software Development Senior Engineer/Technical Manager
MediaTek
HsinChu
5mo
Lead software development for IC (Integrated Circuit) projects, including feature implementation and validation.
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Design Engineering Architect — Memory Modeling Portfolio
Cadence
GYEONGGI-DO (Seoul)
5mo
Senior technical anchor and customer-facing expert for memory protocol IP (UFS/Unipro/MPHY/RMMI) at Cadence, bridging deep protocol knowledge with direct customer partnership to debug, integrate, and deploy complex memory solutions.
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Sr Principal Software Engineer
Cadence
GYEONGGI-DO (Seoul)
5mo
Designing and implementing AMBA protocol functionality, performance verification, and debug tools for emulation and acceleration platforms.
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HSI SW / System development engineer
MediaTek
HsinChu
6mo
Design and validation of HSI system software (drivers/firmware) and hardware (PCB/PHY) for interfaces including USB, PCIe, MIPI, UFS, DP, and HDMI.
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Computing System Architecture Engineer (Benchmark Optimization)
MediaTek
HsinChu
6mo
Analyze benchmarks to identify performance and power bottlenecks, build system models for SoC optimization, and propose actionable system-level improvement strategies.
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Quantum Architect (Design)
PsiQuantum
Palo Alto, California, United States
$120k–$120k
6mo
Designing photonic quantum computing architectures from entanglement generation through encoded logic and error correction to enable million-qubit, fault-tolerant systems.
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Emulation Software Engineer
Etchedai
Software Engineering
6mo
Building high-performance emulation software and tooling to accelerate pre-silicon validation of AI chips (ASICs) designed for specific model architectures like transformers.
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Front-End Power Engineer
Etchedai
Hardware Engineering
6mo
Optimizing RTL designs and power efficiency for AI chips (ASICs) to support high-throughput, low-latency model architectures like transformers.
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Front-End CAD Engineer
Etchedai
Hardware Engineering
6mo
Building and maintaining front-end IC design flows, verification toolchains, and project execution dashboards for AI chip development.
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Digital Design Member of Technical Staff (MTS)
ON Semiconductor
Cork, Co. Cork, Ireland
6mo
Architecting, designing, and integrating complex digital controller IP for power, clock, and error management subsystems within automotive-grade SoCs.
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Senior Principal Software Engineer - Accelerated Verification IP
Cadence
SAN JOSE
$154k–$154k
6mo
Designing, developing, and maintaining PCIe/CXL Accelerated Verification IP (AVIP) and Virtual Bridge (VB) components for high-performance emulation and system verification.
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Lead Software Engineer - AI/LLM for Virtuoso
Cadence
BEIJING
6mo
Designing, implementing, and maintaining software features and interfaces for the Cadence Virtuoso platform to integrate emerging Agentic AI frameworks into electronic design automation tools.
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Application Engineer(Emulation)
Siemens-Eda
Remote
6mo
Senior Application Engineer leading technical engagement for Hardware Assisted Verification (HAV) of digital chip designs using Siemens EDA's emulation and FPGA prototyping products.
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Application Support Engineer - Advanced
Siemens-Eda
Shoreview, MN, United States
$90k–$90k
6mo
Provide advanced technical support and simulation expertise for customers using electromagnetic simulation tools and high-speed digital design.
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Senior Software Engineer, Embedded Algorithm Verification & Automation
Analogdevices
India, Bangalore, Nova
6mo
Automate validation of measurement and monitoring algorithms for power systems and data center infrastructure.
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DFM RET Engineer
Texas Instruments
Dallas, TX, United States
6mo
Develop and deploy Optical Proximity Correction (OPC) models and Design for Manufacturability (DFM) solutions to ensure accurate printing of chip designs at 28nm and below.
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Technical Leader DFT & STA
Cisco
Armenia
6mo
Developing innovative Physical Design methodologies and robust flows for complex ASIC chips, focusing on DFT Timing Engineering and Static Timing Analysis (STA) in test modes.
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Performance Modeling Engineer
MediaTek
San Jose, CA
6mo
Develop performance modeling methodologies and simulation infrastructure to support CPU and SoC architectural exploration and microarchitectural trade-off decisions.
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Principal DV Engineer
MediaTek
San Jose, CA
6mo
Lead verification engineering for a high-end CPU project, focusing on testbench architecture, stimulus generation, and bug triage.
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ICE Graduate Talent
Intel
Malaysia, Penang
6mo
Entry-level program for fresh graduates and early career professionals to join Intel's engineering and technical teams in Malaysia.
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Senior/Staff Engineer, Front End, Central Product Integration
Micron
Hiroshima - Fab 15, Japan
6mo
Senior technical contributor and integration leader enabling robust yield, functionality, and scalability through end-to-end front-end process integration in semiconductor manufacturing.
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