PDK Engineer
Core
Develop, validate, support, and optimize Design Rule Checking (DRC) runsets and rule decks for advanced semiconductor process technology nodes.
Role type
DRC Runset Engineer (Physical Verification)
Builds
Production-quality DRC rule decks and physical verification flows for semiconductor manufacturing
Domain
Semiconductor manufacturing / Physical Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DRC rule deck development, physical verification concepts, layout design rules, debugging, automation, scripting (Python, Perl, Tcl, Shell), test case creation, regression suite maintenance
Preferred skills
AI-based tool usage for rule deck development, end-to-end validation methodologies
Technologies
Siemens Calibre, Synopsys ICV, Cadence Pegasus, Cadence Virtuoso, Calibre DRV, IC WorkBench
Responsibilities
Develop and maintain DRC runsets for advanced nodes; Translate process design rules into efficient physical verification checks; Debug DRC rule deck issues and resolve user-reported problems; Improve runset quality, runtime efficiency, and scalability; Design validation methodologies for DRC runsets and physical verification flows; Support production users with runset-related issues
Seniority
Mid-Senior, hands-on IC
