ASIC Engineer
Core
Develop, maintain, and enhance DFT CAD infrastructure and automation for ASIC design flows.
Role type
Senior IC ASIC DFT Engineer
Builds
DFT implementation flows (Scan insertion, ATPG, SPF, pattern simulation) and automation utilities
Domain
Semiconductor / ASIC Design / Digital Logic
Deliverable
production ML models | product features | dashboards & analysis | infrastructure
Required skills
Verilog/SystemVerilog, DFT/EDA tools, Python/Perl/Tcl/Shell scripting, waveform debugging, regression framework development, job scheduler management (LSF)
Preferred skills
Synopsys Design Constraints (SDC)
Responsibilities
Develop DFT CAD infrastructure and automation; Debug DFT flow failures; Create and maintain regression frameworks and dashboards; Support large-scale regressions on compute farms; Collaborate with DFT Design, ATPG, Verification, and Physical Design teams
Seniority
Senior, hands-on IC
