DRAM IP Development Layout (Internship)
Core
Develop and verify analog and digital IP layout cells for memory products using industry-standard methodologies.
Role type
Layout Design Engineering Intern
Builds
IP layout cells for memory products
Domain
Semiconductor / Physical Design
Required skills
Python, Perl, DRC, LVS, EDA tools (Cadence/Synopsys), scripting
Preferred skills
Semiconductor layout design experience, AI applications in semiconductor development, memory technologies knowledge
Technologies
Python, Perl, Cadence, Synopsys, SKILL
Responsibilities
Develop layout of analog and digital IP cells, Perform DRC and LVS verification, Create technical reports, Design SKILL-based automation solutions, Support AI-assisted development methodologies
Seniority
Intern
