DRAM Layout engineer (Intern)
Core
Develop high-quality physical layouts for cutting-edge DRAM products through semiconductor layout building and physical verification.
Role type
Intern DRAM layout engineer
Builds
Physical layouts for DRAM products
Domain
Semiconductor manufacturing / Memory technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor layout design, Physical verification, EDA tools usage, CMOS technology understanding, Circuit design basics
Preferred skills
Linux environments, Scripting basics, EDA tools familiarity, Programming languages, Physical verification concepts, AI tools for design
Technologies
Cadence, Calibre, Cadence Virtuoso, Synopsys IC Compiler II, Fusion Compiler
Responsibilities
Design and verify all levels of analog and digital layout, Use computer aided design software, Work with Design Engineers to floor plan and design layout, Understand and follow verification protocols, Apply custom and/or automated layout techniques to design pitch, array, and peripheral layout for digital and analog circuits, Collaborate with build engineering to understand layout methodology
Seniority
Intern
