Hardware Verification

1,144 open positions

HBM SOC Design Engineer MicronRichardson, TX 1y Design and development of next-generation HBM DRAM products, focusing on SOC architecture, RTL logic, IP integration, and high-speed interface design.
Modem ESL (Electronic System Level) Modeling Engineer MediaTekHsinChu 1y Developing behavior, cycle-accurate, and power models for next-generation modem and processor architectures.
Fullstack Software Engineer TSMCUSA-Arizona 1y Design, develop, and maintain automation software solutions integrating semiconductor manufacturing equipment with production systems.
Acoustic Engineer （EE） LogitechRemote 1y Select, evaluate, and optimize acoustic components (microphones, speakers) and lead acoustic system design for consumer electronics like keyboards.
Senior Computing Developer AmatBangalore,IND 1y Designing and developing common computing solutions (software/hardware, virtualization, K8s, monitoring) for semiconductor manufacturing machines.
<Data center>SerDes Software and Firmware Senior Engineer MediaTekHsinChu 2y Design and develop SerDes IP firmware and algorithms for high-speed interfaces (50G/100G/200G/300G/400G) to improve system performance and verification coverage.
Sr Principal Design Engineer CadenceBANGALORE, IN 2y Design and support RTL for DDR Memory Controller IP solutions, including DDR4/LPDDR4 protocols.
Design Engineering Manager CadenceBANGALORE 2y Leading pre-silicon physical layer electrical validation infrastructure development and post-silicon validation efforts for High Speed SERDES Test chips.
Digital IC Design Engineer (Performance Verification and Analysis) MediaTekChuPei 2y Develop ESL platforms and simulation/emulation technologies to perform pre-silicon performance sign-off for design teams.
Application Engineer AmatRehovot,ISR 2y Application expert supporting semiconductor manufacturing diagnostics and inspection tools, executing on-site demos, experiments, and technical analysis to maximize tool capabilities for customers.
SystemC/TLM Modeling Engineer (VDK Virtual Platform) MediaTekChuPei 2y Develop high-performance SystemC/TLM virtual platforms to enable software development and integration before hardware availability.
Principal Solutions Engineer - AE CadenceNOIDA 2y Build Virtual/Hybrid prototypes to enable early software development and system validation for customers in electronic design.
Senior/Staff Engineer, Technical Manager (Design Verification) MediaTekSingapore 2y Design verification engineering for Module, IP, and SOC levels using coverage-driven methodologies.
Lead Design Engineer CadenceBANGALORE 3y Lead Design Engineer responsible for functional verification environment development, strategy definition, and deployment for electronic design automation tools.
<Automotive>SoC Interconnect Architect, Designer, and Methodology Developer MediaTekHsinChu 3y Designing high-performance Virtualization and Interconnect Architecture and developing RTL for Automotive and High-Performance Computing.
Senior Java Developer Cross-Border-TalentsVeldhoven, North Brabant, Netherlands 3y Developing modular, scalable, and robust software for high-tech lithography, metrology, and software solutions in the semiconductor industry.
Lead FrontEnd Methodology Engineer CadenceBANGALORE 4y Maintaining and upgrading infrastructure and automation for RTL development and design-verification teams across multiple server farms and cloud environments.
Pre-Silicon Engineer AppleCupertino, United States of America 4y Implement compiler stack features in the ANE simulation environment to enable new hardware features and drive initial chip bring-up.
Modem Digital Design Engineer - Hsinchu/Taipei (5G/6G) MediaTekHsinChu 5y Designing and verifying multi-RAT (6G/5G/4G/3G/2G) modem architectures, digital circuits, and IP integration for SoC systems.
SoC Modeling Engineer MediaTekHsinChu 5y Develop SoC simulation and analysis platform for cell phone and tablet projects to optimize hardware architecture and software control policies for system performance, power, and thermal efficiency.
Lead Application Engineer CadenceSHENZHEN 7y Lead technical evaluations and customer training for Cadence SoC Verification, simulation, emulation, and acceleration products.
INITIATIVBEWERBUNG (M/W/D) Extoll GmbhRemote 8y An initiative-driven role in the Chiplet industry focusing on new technologies and project delivery.
Consultant, AI & Semiconductors SemiAnalysisRemote Conduct technical analysis and research across the semiconductor and AI ecosystem to inform strategic decisions for private equity, venture capital, and government clients.
Hardware Expert (MSc. or PhD), Remote Xperteez TechnologyRemote Create, solve, and evaluate rigorous hardware engineering problems and develop reference solutions using calculations, simulations, and experimental reasoning.
Senior Thermal Engineer Eight SleepSan Francisco $140k–$200k Develop innovative thermal systems for sleep fitness hardware, ensuring industry-leading performance, size, noise, and cost optimization from concept to production.
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Staff Engineer Design Automation (f/m/div) Graz Staff Engineer in Research & Development supporting mixed-signal IC design teams with EDA tools, methodologies, and environment enhancements.
芯片工艺库应用及质量检查工程师-Data（上海） ByteDance上海 Ensures consistency and quality of design kits (Standard cell/SRAM/Macro) through cross-validation, in-flow checks, and full-flow verification for chip design processes.
可靠性工程师（存算与AI） - 芯片研发 ByteDance北京 Design and implement reliability testing for storage-computing AI chips to overcome memory wall bottlenecks and ensure high-efficiency computing for large AI models.
芯片项目质量保证工程师（AI芯片） - 芯片研发 ByteDance北京 Project Quality Representative for AI chip R&D, ensuring quality gates, risk management, and process compliance across the chip development lifecycle.
Staff Engineer Simulation and Package Design Methodology (f/m/div) Infineon Technologies Austria AGVillach Develop and support simulation methodologies, design flows, and tool environments for Chip-Package-Board (CPB) Co-Design and advanced package development in Linux-based HPC environments.
芯片K库工程师（芯片平台） - 芯片研发 ByteDance上海 Chip platform engineer responsible for K-lib (standard cell library) development, quality assurance, and automation for multi-process chip design.
🌍Circuit Design Expert | Remote - Contract Xperteez TechnologyRemote Validating and debugging AI-generated circuit designs for analog, digital, power, mixed-signal, or RF systems using programmatic EDA workflows.
Agent架构工程师（芯片平台） - 芯片研发 ByteDance北京 Design and build an Agent system architecture and runtime platform specifically for IC (chip) R&D, enabling automated design flows from RTL to mass production.
About the job SK Group경기도 이천/ 분당 Building and operating an Omniverse-based Digital Twin platform for semiconductor manufacturing and plant construction, integrating real-time data, simulation, and AI for process optimization and risk management.
🌎 Hardware Expert (MSc. or PhD), Remote- Contract Xperteez TechnologyRemote Create, solve, and evaluate rigorous hardware engineering problems and develop reference solutions using engineering calculations, simulations, and experimental reasoning.
Software Engineer - Parsing (Principal/Staff/Senior) AllSpice.ioBoston / San Francisco $265k–$315k Building a collaboration platform for circuit designs and an agile development framework for hardware designers, including a Git-friendly translation layer and automated CI/CD for native circuit designs.
IC Agent研发工程师（芯片平台） - 芯片研发 ByteDance北京 Building AI Agents to automate and optimize IC design workflows across the full chip development lifecycle (DE/DV/DV/SYN/STA/PD/K-lib/IP).
芯片建模负责人（存算与AI） - 芯片研发 ByteDance北京 Lead the chip modeling team for in-memory computing (存算一体) AI chips, focusing on high-efficiency computing innovation for large AI models to overcome the 'memory wall' bottleneck.
良率工程师（存算与AI） - 芯片研发 ByteDance北京 Yield engineer for in-memory computing (存算一体) AI chips, focusing on high-efficiency computing innovation for large AI models to overcome the 'memory wall' bottleneck.
DFM工程师（存算与AI） - 芯片研发 ByteDance上海 Design and build DFM rule systems for new process platforms in monolithic 3D/存算一体 chips to ensure manufacturability and yield for AI applications.
芯片泛工艺专家-芯片研发 ByteDance西安 Lead process technology evaluation, SPICE device modeling, and PIE integration for AI SoC chips to ensure manufacturability, electrical stability, and yield.
DFT设计工程师（存算与AI） - 芯片研发 ByteDance北京 Define and execute DFT architecture and design for in-memory computing AI chips to address memory wall bottlenecks and improve energy efficiency.
器件开发工程师（存算与AI） - 芯片研发 ByteDance上海 Design and optimize device-level processes for in-memory computing (IMC) AI chips to break the 'memory wall' and improve energy efficiency for large AI models.
研发效能平台开发工程师（存算与AI） - 芯片研发 ByteDance北京 Develop and maintain a full-lifecycle R&D efficiency platform and engineering tools for a chip design team focused on in-memory computing AI chips.

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