Principal Silicon Design Methodology Engineer
Core
Own end-to-end design and qualification of front-end digital IP libraries, ensuring quality across consuming silicon projects and driving multi-project releases.
Role type
Principal Silicon Design Methodology Engineer (Front-end IP)
Builds
Front-end digital IP libraries (standard cells, memories) and qualification/verification pipelines
Domain
Semiconductor / VLSI Design / Digital IC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (IP libraries)
Required skills
RTL/behavioral modeling, static qualification (Lint, CDC, RDC), synthesis, low-power checks, CI/CD pipeline development, IP design simulation and debugging, standard cells mapping, behavioral design modeling, incremental design improvement
Preferred skills
AI-assisted design and verification techniques, technical leadership, mentoring, cross-team technical issue resolution
Technologies
Lint, CDC, RDC, Synthesis tools, EDA tools, CI/CD frameworks
Responsibilities
Drive front-end qualification of library IPs to clean, reproducible releases; Build and maintain qualification and regression pipelines; Act as front-line technical owner for partner-reported issues and integration failures; Partner with SoC design, DV, physical design, and EDA vendor teams; Provide functional leadership to front-end CAD engineers (technical direction, code reviews, mentoring)
Seniority
Principal, hands-on IC with technical leadership
