[2027 Internship] Memory Design Automation Intern
Core
Develop Memory Compiler automation flow and improve data mining/analysis tools for SRAM compiler parameters.
Role type
Memory Design Automation Intern
Builds
In-house memory design kits and design flows for advanced technology nodes
Domain
Semiconductor / Memory Design / EDA
Deliverable
production ML models
Required skills
Physical verification (DRC/ERC/LVS/ANT), Spice simulation (timing/power/noise), QA check, Data analysis, SRAM compiler development
Preferred skills
Data mining
Technologies
SRAM compiler, Spice, DRC, ERC, LVS, ANT
Responsibilities
Improve data mining and data analysis tools for SRAM compiler parameters; Perform physical verification (DRC/ERC/LVS/ANT) on SRAM compiler; Conduct timing, power, and noise Spice simulations on SRAM compiler; Perform QA checks and development on SRAM compiler
