[2027 Internship] Memory Design Automation - Memory modeling
Core
Develop front-end memory design kits (RTL models, ATPG models) and automation flows to support the ASIC design flow and verify memory circuit robustness.
Role type
Intern, Memory Design Automation Engineer
Builds
Front-end memory design kits and automation scripts for ASIC design flow
Domain
Semiconductor, Memory Design, EDA
Required skills
RTL modeling, Perl scripting, Python scripting, EDA tool usage, circuit verification, memory circuit knowledge
Preferred skills
ASIC design flow knowledge, memory IP performance optimization
Technologies
Perl, Python, Synopsys, Mentor Graphics
Responsibilities
Lead development of memory RTL models and ATPG models; Create and optimize automation flows and scripts; Validate model correctness using EDA tools; Ensure functional correctness of memory circuits; Collaborate with design and verification teams; Troubleshoot model issues.
