Standard Cell Design Methodology & Flow Engineer
Core
Designing standard cell libraries and production flows for deep submicron processor designs, integrating custom digital circuits and leveraging machine learning for circuit trend analysis.
Role type
Senior IC standard cell design methodology and flow engineer
Builds
Standard cell libraries, production flows, and verification tools for custom processor designs
Domain
Semiconductor / Digital IC Design / Deep Submicron
Deliverable
production ML models
Required skills
Verilog/SystemVerilog, Python/TCL/Perl, Machine Learning for data analysis, Static Timing Analysis, Power Analysis, Library Characterization, Spice simulation, DFT/Scan concepts, EDA tool integration, Device physics knowledge
Preferred skills
Timing modeling of large custom macros, Complex sequential flop analysis, Flow automation for standard cells, Foundry ecosystem benchmarking, Formal verification, DRC/LVS, RC extraction
Technologies
Verilog, SystemVerilog, Python, TCL, Perl, Spice, Liberty Formats, EDA tools (synthesis, place-route, simulation, formal verification)
Responsibilities
Interface with internal CAD teams and foundries for PDK requirements and production flow planning; Collaborate on new process requirements and enable relevant tools/flows; Implement digital blocks in RTL and run simulations/formal checks; Use ML models to analyze timing, power, and area trends and detect quality issues in large datasets.
Seniority
Senior, hands-on IC
