FEOL RET Process Development Engineer
Core
Translate customer design intent into manufacturable layouts using advanced retargeting techniques to optimize yield, performance, and manufacturability for 28nm/22nm nodes.
Role type
Design Retargeting Engineer (IC)
Builds
Manufacturable IC layouts optimized for lithography and process integration
Domain
Semiconductor manufacturing, advanced node lithography (28nm/22nm)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Design retargeting strategies, OPC/SRA/assist features, EDA tool automation, CD metrology analysis, layout geometry modification, design rule development, semiconductor process integration
Preferred skills
Semiconductor device physics, statistical yield improvement, DTCO, machine learning for layout optimization, DRC/LVS knowledge
Technologies
Synopsis Sentaurus Lithography, Mentor Calibre, ASML Brion, Virtuoso, ICC2
Responsibilities
Develop retargeting strategies to bridge design intent and process capabilities; Collaborate with OPC, lithography, and process integration teams; Analyze and modify layout geometries for printability; Automate retargeting flows with EDA tools; Provide feedback on layout constraints and manufacturability; Perform data analysis using CD metrology, SEM, and simulation; Contribute to design rules for advanced nodes; Mentor junior engineers
Seniority
Senior, hands-on IC