Senior Staff Formal Verification Engineer
Core
Develop and maintain Formal Verification environments for next-generation AMD microprocessors (ASIC/SOC) powering gaming consoles, servers, PCs, and graphics cards.
Role type
Senior Staff IC Formal Verification Engineer
Builds
Pre-silicon IP verification environments, block and IP level test plans, and advanced testbenches for high-complexity RTL designs.
Domain
Semiconductor hardware design and verification
Required skills
Formal Verification (FV), SystemVerilog (SV), UVM, RTL design, coverage analysis, regression testing, ASIC/SOC design flow, test plan creation
Preferred skills
X86/ARM/8051 architecture knowledge, AMBA bus protocols (AXI/AHB/APB), PCIe protocol, SV assertion/coverage/formal verification expertise (6-8 years)
Technologies
SystemVerilog, UVM, Formal Verification tools, RTL simulators
Responsibilities
Apply functional verification techniques to improve pre-silicon IP verification quality; Port/creation of Formal Verification environments; Create and implement block/IP level test plans; Perform coverage analysis and regression cleanup; Provide technical guidance to the FV team
Seniority
Senior Staff, hands-on IC with technical leadership
