Principal Engineer, ASIC Validation
Core
Lead ASIC validation for complete SoC deployment on pre-silicon platforms using ZEBU emulation and Xilinx FPGA flows.
Role type
Principal Engineer, ASIC Validation
Builds
Pre-silicon SoC prototypes and validation plans for memory/storage subsystems (PCIe, LPDDR, ONFI)
Domain
Semiconductor / Memory and Storage / ASIC Design
Required skills
ZEBU emulation, Xilinx Ultrascale FPGA, Vivado Flow, SoC verification, Verilog RTL coding, PCIe/LPDDR/ONFI architecture, VCS simulation, Python/Perl/TCL scripting
Preferred skills
HAPS 100/200, Palladium, Chipscope flow, AI-enabled tools, industry standard interfaces (AXI, NVME)
Technologies
ZEBU, Xilinx Vivado, VCS, HAPS, Palladium, PCIe, LPDDR, ONFI, NVME, AXI
Responsibilities
Complete Xilinx FPGA Flow and Protocompiler Tool flow; Own complete SOC deployment on Pre Silicon platforms; Collaborate with Design/SOC C/FW teams for validation planning; Review and create validation plans for PCIe/LPDDR/ONFI subsystems; Perform Processor based SoC prototyping and Emulation; Run SOC C based simulations for test case understanding and debug using VCS; Write Verilog RTL when required; Debug using Xilinx FPGA Vivado Flow; Work with overseas teams for PCIe/LP bring-up/debug
Seniority
Principal, hands-on IC
