DRAM Verification Engineer, Up to Sr. Staff
Core
Develop and verify next-generation custom DRAM and memory subsystem solutions, ensuring functional correctness, performance, and robust verification closure.
Role type
Senior IC DRAM verification engineer
Builds
Custom DRAM and memory subsystem solutions
Domain
Semiconductor / Memory / Digital Design
Required skills
SystemVerilog, UVM, digital design, simulation, debugging, assertions, coverage-driven verification
Preferred skills
DRAM/DDR/LPDDR/HBM architecture, memory controller interfaces, SVA, formal verification, scripting (Python/Perl/Tcl)
Technologies
SystemVerilog, UVM, SVA, Python, Perl, Tcl
Responsibilities
Develop SystemVerilog/UVM verification environments; Create verification plans, constrained-random tests, checkers, scoreboards, and SVA assertions; Verify DRAM functionality including read/write, refresh, mode registers, initialization, training, timing, and low-power states; Debug RTL and gate-level simulation failures; Partner with design and silicon teams to root-cause issues
Seniority
Senior to Staff, hands-on IC
