ASIC Design Verification Engineer (Security Group) - Sr Staff
Core
Sr Staff ASIC Design Verification Engineer developing and validating secure high-performance subsystems and SoC micro-architectures for Qualcomm products.
Role type
Sr Staff IC ASIC Design Verification Engineer
Builds
Secure SoC subsystems and micro-architectures
Domain
Semiconductor / ASIC Design / Security
Required skills
SystemVerilog, UVM, Synopsys VCS/Verdi, Assertion-based verification, Functional coverage, Python scripting, APB/AHB/AXI protocols, Cryptographic algorithms
Preferred skills
Formal verification, Silicon bring-up, Memory organization, Fault-tolerant design, Error detection/correction, Network-on-Chip Architectures, Mixed signal verification
Technologies
SystemVerilog, UVM, Synopsys VCS, Synopsys Verdi, Python, Makefile, APB, AHB, AXI, SPI
Responsibilities
Develop detailed Test and Coverage plans based on Architecture and Micro-architecture; Develop Verification environment including Stimulus, Checkers, Monitors, Assertions, and Coverpoints; Execute Verification Plans including Design Bring-up, Regression, and Debug; Track and report DV progress using metrics including Bugs and Coverage; Write detailed technical documentation for secure subsystem designs; Run and Analyze Coverage reports to identify holes and re-spin Test Plans.
Seniority
Sr Staff, hands-on IC with mentorship
