MSIP Design Verification Engineer - Cork, Ireland
Core
Mixed-Signal Design Verification Engineer developing verification environments for SerDes, DDR, PLL, and other PHY IPs in next-generation Snapdragon SoCs.
Role type
Senior IC mixed-signal design verification engineer
Builds
Production mixed-signal PHY IP blocks (DDR, USB, PCIe, eDP, HDMI, etc.) for Snapdragon SoCs
Domain
Semiconductor / Mixed-Signal ASIC Design
Required skills
SystemVerilog, UVM, constrained random verification, assertion-based verification, formal verification, Python/TCL/Perl/shell scripting, UPF (low power), gate-level simulation (GLS), ATE/PTE vector bringup, RTL and analog/mixed-signal design verification
Preferred skills
Emulation experience, analog mixed-signal verification techniques
Technologies
SystemVerilog, UVM, Python, TCL, Perl, Shell, UPF, ATE, PTE
Responsibilities
Develop SV/UVM based design verification environments for SerDes, DDR & PLL Mixed-Signal PHY IP; Work closely with analog and digital front-end design teams to verify RTL and Analog/Mixed-Signal Designs; Interact with architecture, design, physical design, software, test and SoC teams to verify and integrate IP designs into Snapdragon products
Seniority
Senior, hands-on IC
