DDR Design Verification Lead Engineer
Core
Lead Design Verification (DV) engineer for LPDDR/DDR based IPs and Subsystems in the Infra IP team.
Role type
Senior IC digital design verification engineer (memory protocols)
Builds
High performance, high quality, low power world class products (ASICs/SoCs)
Domain
Semiconductors / Memory Interfaces (DDR/LPDDR)
Required skills
System Verilog, UVM, Debug, Test plan creation, Coverage analysis, Bus protocols (AHB/AXI/ACE/ACE-Lite), Digital design concepts, DV methodologies and tools
Preferred skills
DDR/LPDDR families and generations (DDR2/3/4/5), VIP integration, Monitor/Scoreboard/Sequencer development, Scripting
Technologies
System Verilog, UVM, VIPs, AHB, AXI, ACE, ACE-Lite
Responsibilities
Create DV infrastructure for verification, Integrate VIPs, Create and execute test plans, Debug failures, Write assertions, Close code and functional coverage
Seniority
Senior, hands-on IC
